1. Field of the Invention
This invention generally relates to a microprocessor system for generating instruction addresses therein and more particularly to a microprocessor system which can generate instruction addresses therein at a high speed.
2. Description of the Related Art
Referring first to FIG. 7, there is schematically shown a part, which is most directly related to the generation of an instruction address during the execution of a branch instruction, of a branch instruction processing portion of a conventional microprocessor system.
An arithmetic logic unit (ALU) 4 for generating flags generates a flag 14, the contents of which comprise four composing flags, that is, a carry flag, a zero flag, a negative flag and an overflow flag, and then outputs the flag 14 to a status register 2. Further, the status register 2 is controlled by a flag update detecting signal 11 outputted from a flag update detector 1 and stores the contents of the contents of the flag 14 when an arithmetic or logical operation instruction for updating a flag is executed. A predicate evaluation circuit 3 determines whether or not a branch is taken, based on both of a flag 12 outputted by the status register 2 and a branch condition 15 which is the contents of a branch condition field 10a of an instruction 10. Further, the predicate evaluation circuit 3 outputs a branch taking notice signal 13 indicating the result of the determination to an address selecting circuit 5 whereupon a target instruction address 16 and a next instruction address 17 are selected. Then, the address selecting circuit 5 outputs one of these addresses as an instruction fetch address 20.
Turning now to FIG. 9, there is shown another known conventional system for generating an instruction address. This conventional system determines whether or not a branch is taken, based on the flag 14 outputted from the ALU 4 in case where an instruction immediately prior to a conditional branch instruction updates the flag and on the other hand based on the flag 12 outputted from the status register 2, which stores a flag reflecting the result of the last executed operation instruction updating the flag, in case where an instruction immediately prior to a conditional branch instruction does not update the flag. Then, this conventional system determines an instruction address in accordance with the result of the determination. In this conventional system, a flag update detector 1 determines whether or not the flag is to be updated. Further, in accordance with a flag update detecting signal outputted from the flag updating detector 1, a flag selecting circuit 7 chooses one of the flag 12 outputted from the status register 2 and the flag 14 outputted from the ALU 4 and outputs the chosen flag 12 or 14 to the predicate evaluation circuit 3. This predicate evaluation circuit 3 receives the flag chosen by the flag selecting circuit 7 and a branch condition 15 which is the content of a branch condition field 10a of an instruction 10 as inputs thereto and then determines whether or not a branch is taken. Further, the predicate evaluation circuit 3 notifies the address selecting circuit 5 of the result of the determination by using a branch taking notice signal 13. The address selecting circuit 5 then selects a target instruction address 16 and a next instruction address 17 and further outputs an instruction fetch address 20.
However, in the conventional system of FIG. 7, when a program is executed in the order of, for example, an arithmetic or logical operation instruction, a conditional branch instruction, a delay instruction and a target instruction, in case where an operation instruction directly prior to a conditional branch instruction updates a flag as ADDcc (i.e. ADD and modify condition code) does in pipeline processing comprising four stages (namely, an instruction fetching stage, an instruction decoding stage, an instruction executing stage and an execution result storing stage as shown in FIG. 8), the flag 14, which reflects the result of the arithmetic or logical operation and is used for determining whether or not a branch is taken, is not stored in the status register 2 in a stage of determining whether or not a branch condition of a branch instruction is met (i.e. the instruction decoding stage for decoding a conditional branch instruction). This is because the flag 14 reflecting the result of the arithmetic operation is written into the status register 2 in the execution result storing stage. Further, this results in that the performing of the instruction decoding stage of decoding the conditional branch instruction is put off for one machine cycle until the execution result storing stage for storing the result of the execution of the operation instruction updating the flag is performed. Thus, 2 machine cycles all told are necessary for executing a conditional branch instruction. This is called "register interlock" and causes a disturbance in the pipeline and thus becomes an important factor of deterioration of performance of the microprocessor system.
On the other hand, in the conventional system of FIG. 9, a rate-determining path up to the output of the instruction fetch address 20 generates the flag 14 reflecting the result of the arithmetic or logical operation by using the ALU 4 and determines whether or not a branch is taken, based on the flag 14, and further selects the target instruction address 16 and the next instruction address 17 in accordance with the branch taking notice signal 13 and finally outputs the instruction fetch address 20. Furthermore, in this conventional system, it is necessary to choose one of the flag 12 outputted from the status register 2 and the flag 14 outputted from the ALU 4 in the flag selecting circuit 7. Therefore, this conventional system has a drawback that the generation of the branch taking notice signal 13 is delayed by connecting the flag selecting circuit 7 to the rate-determining path in series and thus the choice of the target instruction address 16 and the next instruction address 17 cannot be performed at a high speed.
Additionally, though each of the above described conventional systems has a single predicate evaluation circuit and thus the circuit of each of the above described conventional systems has a simple structure, it is very difficult for the conventional systems to realize high speed generation of flags and high speed predicate evaluation. As a case in which a rate-determining stage of the predicate evaluation processing is time-consuming, can be cited the processing in the case that the branch condition is "greater", "greater or equal", "less or equal" or "less". Namely, in such cases, an exclusive-OR of the negative flag and the overflow flag is generated and thus the number of processing stages is larger than that of the processing stage in case of the other branch conditions in which the processing can be performed by using a single-stage gate corresponding to NOT (logical negation), OR (logical sum) and so on. Further, in such cases, by using the exclusive-OR of the negative and overflow flags, it is determined whether or not a branch is taken, and therefore the branch taking notice signal 13 is delayed. Thus, the conventional systems above described have a drawback that it is difficult to perform the choice of the target instruction address 16 and the next instruction address 17 at a high speed.
The present invention is accomplished to eliminate the drawbacks of the conventional systems.
It is accordingly an object of the present invention to provide a microprocessor system which can output a instruction fetch address at a high speed.